1. Field of the Invention
The present invention relates to a ring oscillator used in a memory device adopting a charge pump and an on-chip timer; and, more particularly, to a ring oscillator including a comparator as a unit chain cell and, therefore, capable of minimizing its current consumption and rapidly changing a frequency of its output signal in response to a level change of a source voltage.
2. Description of the Prior Art
Referring to FIG. 1, there is provided a conventional ring oscillator which comprises an inverter chain unit 10 and an output buffering unit 12. The inverter chain unit 10 includes a plurality of inverters I1 to I4 connected in series; a NAND gate NAND1 whose two input terminals receive an output signal from the inverter I4 and external clock signal clk, respectively, and output terminal is connected to an input terminal of the inverter I1 via a second node N2. The output buffering unit 12 has a multiplicity of inverters, e.g., I5 and I6, connected in series, wherein an input terminal of the inverter I5 is connected to a first node N1 linking the output terminal of the inverter I4 and one of the input terminals of the NAND gate NAND1; and buffers the output signal of the inverter chain unit 10 to thereby provide the buffered output signal as its output signal osc1.
Hereinafter, the operation of the conventional ring oscillator shown in FIG. 1 will be illustrated.
First of all, if an external input control signal, i.e., the external clock signal clk, which is fed to the inverter chain unit 10 has a logic low state, the output signal of the NAND gate NAND1 maintains a logic high state since the NAND gate NAND1 is disabled. That is, the second node N2 has a logic high state. As a result, the output signal osc1 of the output buffering unit 12 which is connected to the inverter chain unit 10 via the first node N1 also maintains a logic high state and, therefore, there is no output pulse signal generated from the ring oscillator.
On the other hand, if the clock signal clk having a logic high state is inputted to the inverter chain unit 10, the NAND gate NAND1 is enabled and the output signal of the NAND gate NAND1, having an inverted level of an input voltage fed to the NAND gate NAND1 via the first node N1, is provided at the second node N2. As a result, a pulse signal having a predetermined frequency is generated from the NAND gate NAND1 as the voltage level of the first node N1 is continuously inverted. Also, the pulse signal generated at the first node N1 is buffered by the inverters I5 and I6 in the output buffering unit 12 and then outputted as the output pulse signal osc1.
However, the conventional ring oscillator consumes a substantial amount of current through the inverter chain unit 10 when the external clock signal clk has a logic high state and cannot perform a rapid frequency change following the source voltage change.